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Senior Methodology Engineer – Physical Design Automation

Job in Greater London, London, Greater London, W1B, England, UK
Listing for: Aion Silicon Ltd
Full Time position
Listed on 2026-10-15
Job specializations:
  • Engineering
    Automation & Mechatronics Engineer, Systems Engineer, Data Engineering
Salary/Wage Range or Industry Benchmark: 90000 - 120000 GBP Yearly GBP 90000.00 120000.00 YEAR
Job Description & How to Apply Below

We are seeking a highly motivated Senior Methodology Engineer to drive the development of advanced Physical Design automation, methodologies, and quality systems for complex SoC and ASIC designs. The ideal candidate will combine strong expertise in the RTL-to-Signoff Physical Design flow with software development skills to build scalable automation frameworks, improve design productivity, and enable high-quality silicon delivery across advanced process technologies.

Key Responsibilities

Develop and maintain automation frameworks supporting the complete RTL-to-Signoff Physical Design flow
.

Build methodology solutions for synthesis, floor planning, power planning, placement, CTS, routing, timing closure, and signoff.

Create quality checking, validation, and reporting systems for implementation and signoff metrics.

Develop scalable tools, scripts, and data pipelines for design analysis, productivity enhancement, and methodology optimization.

Collaborate with Physical Design, STA, DFT, RTL, Library, and CAD teams to improve implementation methodologies and design quality.

Drive continuous improvements in timing, power, area, congestion, IR/EM, and physical verification closure.

Define and maintain best practices, design guidelines, and signoff methodologies across multiple projects.

Support advanced-node implementation challenges through innovative automation and data-driven solutions.

Required /

Preferred Qualifications

Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.

4+ years of experience in Physical Design, CAD Methodology, or Design Automation.

Strong understanding of the complete ASIC/SoC implementation flow from RTL to GDSII Signoff.

Hands-on experience with industry-standard EDA tools and flow customization.

Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).

Strong knowledge of hierarchical and top-down design methodologies.

Experience in Physical Design flow automation, CAD infrastructure, and methodology development.

Exposure to AI/ML or LLM-based solutions for EDA automation and productivity enhancement.

Excellent problem-solving, debugging, and cross-functional collaboration skills.

Tools & Skills

Cadence: Innovus, Tempus, Voltus, Pegasus

Programming: Python, Tcl, Perl, Shell, C++

Automation: Workflow development, data pipelines, quality dashboards, methodology deployment

Position Requirements
10+ Years work experience
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