Power Integrity & EMIR Engineer SoC Signoff
Listed on 2026-10-16
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Engineering
Electronics Engineer, Systems Engineer, Electrical Engineering, Hardware Engineer
Aion Silicon Ltd is seeking an experienced EMIR / Power Integrity Engineer to join the SoC Physical Design team in London. You will own PDN planning, EMIR verification, and signoff for advanced semiconductor designs, driving ECOs and signoff closure.
Responsibilities include PDN optimization, IR drop analyses, EMIR signoff, and automation of flows using scripting languages. Collaboration across Physical Design, RTL, Package, and Reliability is essential.
Join us at Aion Silicon Ltd as our next Power Integrity & EMIR Engineer for SoC Signoff in Greater London, England, United Kingdom.
The position is based in Greater London, England, United Kingdom.
This opportunity is part of our work in Engineering.
The advertised compensation is 90..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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