AI Accelerator Architect

We are seeking an experienced Principal ASIC Design Engineer to contribute to the architecture, microarchitecture, and RTL development of next-generation AI accelerators and high-performance SoC subsystems.

The ideal candidate will have extensive hands-on design experience in GPU, NPU, or complex SoC subsystems, with a proven track record of delivering advanced ASIC products from initial specification through RTL implementation, verification, physical design, silicon bring-up, and production.

This position focuses on hands-on engineering, complex digital design, performance optimization, and implementation of advanced computing and interconnect architectures.

• Develop architecture and microarchitecture for high-performance AI accelerators and complex SoC subsystems.
• Translate system-level requirements into detailed functional and microarchitecture specifications.
• Design compute pipelines, memory hierarchies, on-chip interconnects, DMA engines, and data movement architectures.
• Evaluate design trade-offs involving performance, power, area (PPA), memory bandwidth, latency, and scalability.
• Collaborate with system architects, algorithm engineers, and software engineers to optimize hardware implementations for AI/ML workloads.

• Develop detailed microarchitecture specifications and synthesizable RTL implementations using Verilog/System Verilog.
• Design complex digital datapaths, control logic, finite state machines, arbitration mechanisms, and communication interfaces.
• Implement efficient pipelining, buffering, flow control, and resource-sharing mechanisms.
• Optimize RTL for timing, power, area, and implementation feasibility.
• Perform RTL simulation, debugging, lint, clock-domain crossing (CDC) analysis, and synthesis-related design checks.
• Work with verification and physical design engineers to resolve functional, timing, and implementation issues.

• Design and integrate high-bandwidth memory and high-speed I/O subsystems.
• Work with memory interfaces and controllers, including LPDDR5/LPDDR5X and LPDDR
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• Design or integrate PCIe-based subsystems, including PCIe Gen5/Gen6 controllers, DMA engines, and associated data movement infrastructure.
• Understand NoC architectures, memory hierarchies, cache coherency, and bandwidth optimization.
• Optimize data movement and memory access efficiency for high-performance computing and AI accelerator applications.

• Participate in the complete ASIC development lifecycle, from specification and microarchitecture through RTL design, verification, synthesis, physical implementation, tape-out, and silicon validation.
• Develop production-quality RTL that meets functional, performance, power, and area requirements.
• Collaborate with verification engineers on block-level and SoC-level verification plans, test cases, and functional coverage.
• Support lint, CDC/RDC analysis, formal verification, synthesis, static timing analysis, and design-for-test activities.
• Debug functional and timing issues identified during simulation, emulation, FPGA prototyping, and physical implementation.
• Support silicon bring-up, post-silicon debugging, performance characterization, and production validation.

• Collaborate with firmware, driver, compiler, and system software engineers to define and implement hardware/software interfaces.
• Participate in hardware/software partitioning and optimization for AI accelerator applications.
• Develop register interfaces, control/status mechanisms, interrupt handling, and system-level data flows.
• Support IP-level and SoC-level functional verification using…