SoC Physical Design Lead – Tape- Expert

Aion Silicon Ltd in Greater London seeks a Principal Engineer – SoC Physical Design to lead ASIC/SoC tape-out and integration from architecture to silicon. You will drive full-chip physical implementation, floor planning, power/clock distribution, timing closure, and signoff, collaborating with Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

The role requires 15+ years in ASIC/SoC physical design, a track record of multiple tape-outs, and strong leadership

We invite applications for the SoC Physical Design Lead – Tape-out Expert position located in Greater London, England, United Kingdom.

The advertised compensation is 110..

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the SoC Physical Design Lead – Tape-out Expert role in the description above.