Lead Verification Engineer

Exciting opportunity for a Lead Verification Engineer to help establish a new European engineering team, bringing existing DV colleagues or building a team from the ground up within the RISC-V and open-source silicon space.
Build a New European Digital Verification Team - Permanent Opportunity
The Opportunity  We are partnering with an innovative technology organisation operating at the forefront of RISC-V, open-source silicon, secure hardware and processor IP, with strong links to the lowRISC ecosystem.
The business is looking to establish a new European Digital Verification function and is seeking an experienced  Lead Verification Engineer  to play a key role in building the team, driving technical direction and overseeing verification activities.

Location:

Anywhere in Europe, with flexibility to establish a new engineering office based on the strength and availability of the team.

The Role  You will provide hands-on technical leadership, helping establish and develop the European DV team while working closely with wider engineering teams across Europe.
Responsibilities will include:
Providing technical leadership across ASIC / SoC Digital Verification.
Driving verification strategy, planning and execution.
Leading System Verilog and UVM testbench development.
Overseeing functional coverage, debug and verification closure.
Mentoring and supporting Senior and Verification Engineers.
Collaborating with RTL design, architecture and engineering teams.
Helping recruit, develop and grow the European DV function.
We Are Particularly Interested In   Experienced Lead Verification Engineers currently working within an established DV team.
Individuals who could introduce and bring together experienced Digital Verification Engineers.
Technical leaders with the ability to build and develop a high-performing verification team.
Technical Background   ASIC / SoC Digital Verification.
Strong System Verilog and UVM.
Functional Verification and Coverage Closure.
Formal Verification.
RISC-V processor and SoC verification.
Experience leading verification projects or mentoring DV engineers.
Why Consider This?  A unique opportunity to help establish a new European verification team, bring existing colleagues or build one around you, and play a key role in the technical direction of an organisation working within the RISC-V and open-source silicon ecosystem.
Interested in Finding Out More?  I am keen to connect with experienced Lead Verification Engineers, particularly those who are already part of an established DV team or have a network of engineers they could introduce.