Senior Software Engineer – Ultra Low Latency Risk Engine Developer

- Senior Software Engineer – Ultra Low Latency Risk Engine Developer

Overview

Citi Equities Technology | Equities Electronic Execution (Electronic Trading)

Citi's Equities Technology organization is seeking a Senior Software Engineer – Ultra Low Latency Risk Engine Lead Developer to join the Equities Electronic Execution (Electronic Trading) technology team. This role is focused on the design, development, and delivery of Citi's next-generation low-latency Risk Engine for cash equities and its integration into the broader execution platform — encompassing the Centralised Position Service, Client Connectivity, Market Access layers, and high-throughput market data processing.

Role Overview

The engineer will own critical, latency-sensitive risk-checking components that sit directly in the cash equities trading hot path, ensuring pre-trade and real-time risk controls are enforced with microsecond-level performance while maintaining correctness and resiliency s is a hands-on, deeply technical role that also carries leadership responsibilities — mentoring engineers, driving architecture decisions, and coordinating delivery across global development centers.

The person will collaborate closely with product development, quantitative research, technology infrastructure, production support, and QA teams, with close alignment to global strategy and cross-regional delivery (APAC, EMEA, NAM).

Risk Engine & Core Development

• Design, develop, and maintain the ultra-low-latency, in-line Risk Engine responsible for real-time pre-trade risk checks, position limits, and exposure controls across cash equities electronic execution flows.
• Architect and optimize high-performance, lock-minimal, multi-threaded components capable of processing risk decisions in the sub-microsecond to low-microsecond range.
• Integrate risk and position components with Client Connectivity, Market Access layers, and high-throughput market data feed handlers.
• Design and implement low-latency messaging and IPC architectures using technologies such as Aeron and Solace, along with shared-memory/IPC mechanisms, to enable fast, reliable communication between distributed risk, execution, and position components.
• Apply deep expertise in JVM performance tuning, memory management, garbage collection avoidance, and/or native (C++/Rust) performance engineering to eliminate latency outliers (“jitter”) in the risk path.
• Perform system-level performance tuning including NUMA-aware application design and memory allocation, CPU core isolation/pinning and affinity tuning, interrupt/IRQ tuning, and kernel bypass or low-latency networking techniques (e.g., kernel bypass stacks, RDMA, solarflare/onload-style NIC tuning) to minimize end-to-end latency and jitter across the risk and execution path.

Product & Cross-Functional Collaboration

• Partner with cash equities traders, quantitative researchers, and clients to translate risk, exposure, and control requirements into robust engineering designs.
• Work with market access teams to ensure risk checks are correctly and efficiently embedded across order lifecycle events (new, amend, cancel) and multiple execution venues.
• Support new liquidity source onboarding and DMA capability enhancements from a risk-controls perspective.

Testing & Quality Engineering

• Build and continuously improve deterministic, repeatable testing frameworks (unit, integration, latency/performance, and chaos/failover testing) tailored to ultra-low-latency risk systems.
• Champion test-driven development (TDD) practices for mission-critical, heavily multi-threaded, asynchronous components.
• Establish performance benchmarking and latency regression testing — including messaging, network, CPU, and memory subsystem profiling — as part of the standard delivery…