Senior Ultra-Low Latency C++ Engineer; FPGA)

JPMorgan Chase is seeking an Ultra Low Latency C++ Lead Software Engineer within the Electronic Trading Technology team. You will design, build, and operate market gateway solutions with hardware FPGA acceleration, driving latency optimization and reliability across global markets.

You will lead the development of market access trading and risk management modules, collaborating with hardware teams to integrate FPGA pipelines with the C++ software stack and ensuring secure, scalable production

The following opening is for a Senior Ultra-Low Latency C++ Engineer (FPGA) with JPMorgan Chase & Co.

This is a great role to take on the Senior Ultra-Low Latency C++ Engineer (FPGA) role at JPMorgan Chase & Co.

As a Senior Ultra-Low Latency C++ Engineer (FPGA), you will play an important part at JPMorgan Chase & Co. in Greater London, England, United Kingdom.