Timing Design Engineer; Part‑Time
Listed on 2026-10-27
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Engineering
Apple in Sacramento, CA is seeking a Timing Design Engineer on a part-time basis. The role focuses on block-level static timing analysis, clock networks, and timing closure for high-performance SOCs. Strong Verilog and STA experience are required.
You will collaborate with RTL/PD teams, generate ECOs, and help refine CAD methodologies while benefiting from comprehensive health, retirement, and stock options. Apple emphasizes growth support and educational reimbursements.
The Timing Design Engineer (Part‑Time, $28/hr) position in the Management & Operations field is open for applications.
This is a genuine role to take on the Timing Design Engineer (Part‑Time, $28/hr) role at Apple.
As a Timing Design Engineer (Part‑Time, $28/hr), you will play an important part at Apple in Sacramento, CA, United States.
We invite applications for the Timing Design Engineer (Part‑Time, $28/hr) position located in Sacramento, CA, United States.
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