Senior Defect Modeling & 3D Packaging Lead
Listed on 2026-10-30
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Engineering
Packaging Engineer, Manufacturing Engineer, Process Engineer, Quality Engineering
TSMC
- Taiwan Semiconductor Manufacturing Company Limited in San Jose, CA seeks an experienced engineer to advance defect modeling, testing, and analysis for next‑gen 2.5D/3D packaging. This role emphasizes developing models, running SPICE simulations, and collaborating with design, process, test, and reliability teams to push innovative approaches.
You will contribute to methodologies for defect detection, test strategy optimization, and industry-leading packaging solutions, with visa
As a Senior Defect Modeling & 3D Packaging Lead, you will play an important part at TSMC
- Taiwan Semiconductor Manufacturing Company Limited in CA, United States.
We are currently recruiting a Senior Defect Modeling & 3D Packaging Lead for our team in CA, United States.
This is a great role to take on the Senior Defect Modeling & 3D Packaging Lead role at TSMC
- Taiwan Semiconductor Manufacturing Company Limited.
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