RISC-V CPU Front-End Physical Lead - RTL & PPA Expert
Listed on 2026-10-30
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Tenstorrent is seeking an engineer to lead the front-end RTL physical implementation for a high‑performance RISC‑V CPU. You will drive CAD flows, define floor plans, and collaborate with microarchitecture, RTL, and PD teams to optimize frequency, power, and area.
This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience and a compensation package reflecting base and variable components.
This role, RISC-V CPU Front-End Physical Lead - RTL & PPA Expert at Tenstorrent, could be your next opportunity.
All applications are reviewed carefully by our team.
The position is based in CA, United States.
This opportunity is part of our work in Management & Operations, Engineering.
The advertised compensation is 100..
We aim to respond to suitable candidates as soon as possible.
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