FPGA RTL Design Engineer

PGA RTL Design Engineer

design, develop, and debug hardware algorithms to help implement an advanced wireless communications prototype.

• 5+ years implementing complex digital designs in programmable logic using FPGA devices, or equivalent experience in ASIC design
• Experience with Verilog, System Verilog and HDL-based design verification including regression testing.
• Thorough knowledge of FPGA architecture including experience with advanced floor‑planning and timing closure techniques.
• Experience with SoC bus interconnect protocols such as AXI4, streaming AXI and AHB.
• Experience with industry‑standard high‑speed interfaces such as DDR4, 10/40/100 GbE, PCIe and Interlaken.
• Experience with bring up and lab debugging of complex FPGA designs.
• Experience with wireless standards such as 4G, 5G  Wi‑Fi.
• Familiar with embedded software/firmware design, especially in complex debugging of on‑target SW/HW interaction.

• MS Electrical Engineering, Computer Engineering, or a closely related field
• 8+ years implementing complex digital designs in programmable logic using FPGA devices, or equivalent experience in ASIC design
• Knowledge of FPGA design environments including Vivado, Modelsim, and MATLAB
• Experience using these techniques with Xilinx Ultra Scale/Ultra Scale+ FPGA families
• Familiarity with C, C++, or Python
• Experience working with IEEE-1588 PTP time synchronization and 802.3 Ethernet protocols