RISC-V CPU Front-End Physical Lead - RTL & PPA Expert
Listed on 2026-10-18
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Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer
Tenstorrent is seeking an engineer to lead the front-end RTL physical implementation for a high‑performance RISC‑V CPU. You will drive CAD flows, define floor plans, and collaborate with microarchitecture, RTL, and PD teams to optimize frequency, power, and area.
This hybrid role is based in Austin, TX or Santa Clara, CA, with offers aligned to experience and a compensation package reflecting base and variable components.
As a RISC-V CPU Front-End Physical Lead - RTL & PPA Expert, you will play an important part at Tenstorrent in California, MO, United States.
We invite applications for the RISC-V CPU Front-End Physical Lead - RTL & PPA Expert position located in California, MO, United States.
The following role is for a RISC-V CPU Front-End Physical Lead - RTL & PPA Expert with Tenstorrent.
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