Senior FPGA RTL Design Engineer Wireless Prototypes

ALTEN is looking for a PGA RTL Design Engineer in California, MO to design and develop hardware algorithms for advanced wireless communications. The ideal candidate will have 5+ years of experience in FPGA or ASIC design and be proficient in Verilog and System Verilog.

The role involves debugging complex FPGA designs and developing solutions for high-speed interfaces such as DDR4 and PCIe. Join our innovative team to contribute to cutting-edge wireless technologies!

Consider building your career as a Senior FPGA RTL Design Engineer for Wireless Prototypes at ALTEN.

We invite applications for the Senior FPGA RTL Design Engineer for Wireless Prototypes position located in California, MO, United States.

The following opportunity is for a Senior FPGA RTL Design Engineer for Wireless Prototypes with ALTEN.

Our team is growing, and we are hiring a Senior FPGA RTL Design Engineer for Wireless Prototypes in California, MO, United States.