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Senior Design Verification Engineer – CPU Subsystem
Job in
Los Angeles, Los Angeles County, California, 90001, USA
Listed on 2026-10-18
Listing for:
ALTEN
Full Time
position Listed on 2026-10-18
Job specializations:
-
Engineering
Test Engineer, Validation Engineer
Job Description & How to Apply Below
Experience: 5–12+ Years
Responsibilities- Verify CPU subsystem and standard interfaces using System Verilog/UVM.
- Develop verification plans, UVM test benches, test cases, assertions (SVA), and functional coverage.
- Verify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling.
- Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
- Collaborate with Architecture, RTL, and Validation teams through verification signoff.
- Strong System Verilog/UVM expertise.
- Experience verifying CPU subsystems or SoC integration.
- Good understanding of AXI/AHB/APB and standard SoC interfaces.
- Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
- Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).
We have an opening for a Senior Design Verification Engineer – CPU Subsystem in California, MO, United States within Engineering.
All applications are reviewed carefully by our team.
The position is based in California, MO, United States.
Position Requirements
10+ Years
work experience
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