Senior Architect

IC Resources is working with a well funded photonics company developing next generation optical interconnect technology for AI and high performance computing infrastructure.

The company is developing highly integrated optical engine technology designed to address the bandwidth limitations emerging between GPUs, accelerators, and memory in next-generation AI systems.

They’re looking for a senior technical leader to own the architecture, definition, and multi chip integration of next generation optical engines. This is a highly cross functional role spanning optical link architecture, silicon photonics, high speed analog/mixed-signal silicon, Ser Des, advanced packaging, and system integration.

You’ll act as the technical bridge between product requirements and engineering execution, translating MRDs into detailed PRDs and driving the optical engine from architecture through silicon, integration, validation, and system bring up.

• Own the architecture and technical definition of high-speed optical engines
• Translate market requirements into detailed product and engineering requirements
• Define end to end optical link budgets and model dispersion, noise, laser RIN, link penalties, and FEC trade-offs
• Architect optical engines around emerging OCI-MSA requirements
• Work closely with PIC teams on high-speed silicon photonic components including micro ring modulators, photodetectors, and MUX/DEMUX structures
• Define critical electrical/optical interfaces between PICs and high-speed drivers/TIAs
• Work across silicon photonics foundry processes, PDK constraints, DRC/LVS, and tape out readiness
• Provide technical leadership across high-speed EIC development, including modulator drivers, TIAs, NRZ/PAM4 Ser Des, clocking, power, and thermal architecture
• Oversee full chip development and tape out execution
• Drive 2.5D integration and co-packaging strategies across PICs, EICs, interposers, and optical interfaces
• Work with OSAT partners on assembly, substrates, and manufacturing methodology
• Lead post-silicon characterization including BER, jitter, and eye diagram performance
• Support system bring up, ATE strategy, and integration into next-generation AI networking platforms

The critical requirement is previous experience architecting or delivering high-speed optical links, optical engines, optical compute interconnects, or closely related optical transceiver technology. This is not simply a PIC design position.

• 7+ years of semiconductor, photonics, or optical-interconnect engineering experience
• Strong optical link / optical engine architecture experience
• Deep understanding of high-speed silicon photonics
• Experience with active modulators and photodetectors
• Strong understanding of PIC/EIC co-design
• Experience with high-speed analog drivers and TIAs for optical transceivers
• Knowledge of NRZ and PAM4 Ser Des
• Experience with advanced node semiconductor technology
• Ability to operate across optical, electrical, packaging, and system level boundaries

• Experience with 2.5D integration, flip-chip assembly, high density interposers, micro bumps/copper pillars, and co-packaged optical architectures would be highly valuable.
• Familiarity with engineering environments such as Ansys Lumerical, Opto Compiler, IPKISS, Cadence EPDA, OptoSPICE, Virtuoso/Spectre, Innovus, or equivalent flows is also relevant.
• Previous architecture or design experience within a leading semiconductor, optical networking, or high-speed connectivity organization is strongly preferred.

This is an opportunity to have significant architectural ownership over a new generation of optical interconnect technology being developed specifically for the bandwidth and power requirements of AI infrastructure.

If your background sits at the intersection of optical engines + silicon photonics + high-speed silicon + optical link architecture, I’d be interested in speaking confidentially.