Digital Design Engineer; Graduate

Location:

United Kingdom

Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting‑edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity.

For more information about us, check out our website (Analogue Insight) and Linked In Page (Analogue Insight™: Overview | Linked In).

We are seeking a talented and motivated Graduate Digital Design Engineer to join our team and contribute to the design and verification of digital and mixed‑signal IP for our chiplet solutions, including PCS (Physical Coding Sublayer) logic and custom high‑speed interfaces such as UCIe, Ethernet and PCIe. Working alongside experienced digital and analog engineers, you will write RTL, build test benches and behavioural models, and see your work go into customer silicon.

This role is well suited to recent graduates with a strong foundation in digital design who want to learn fast through hands‑on work in a small, high‑impact team.

Hiring Manager: Christian Borelli, Founder and CSO.

• RTL Design:
  Design and implement digital blocks for PCS and interface IP (e.g. encoders/decoders, scramblers, PRBS generators/checkers, FIFOs, CDC logic, control and calibration state machines) in Verilog/System Verilog, under the guidance of senior designers.
• Standards & Specifications:
  Study Ser Des and UCIe standards and architecture documents, and help turn them into clear block‑level specifications.
• Verification:
  Build test benches and run simulations to verify your designs, using System Verilog, UVM or cocotb, and help develop verification plans and coverage.
• Mixed‑Signal Modelling:
  Write behavioural models of analog blocks in Verilog/System Verilog (and Verilog‑A where needed) to support mixed‑signal and top‑level simulation with the analog team.
• Implementation Support:
  Gain exposure to synthesis, lint, CDC checks and static timing analysis, and learn how design choices affect power, performance and area.
• Scripting & Automation:
  Use scripting (e.g. Python, TCL or shell) to automate simulation, regression and reporting flows.
• Documentation & Process:
  Document your designs and test results clearly, and contribute ideas to improve our design and verification environments and procedures.
• Collaboration:
  
  Work closely with an experienced team of digital, analog and layout engineers across products such as UCIe, Ethernet and PCIe.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field (recent graduates and those graduating within the next 6 months are welcome)
• 0–2 years of experience in digital design, including internships, placements or university projects
• Solid understanding of digital logic fundamentals: synchronous design, finite state machines, timing, pipelining and clock‑domain crossing
• Hands‑on experience writing RTL in Verilog or System Verilog, through coursework, thesis, FPGA or internship projects
• Experience with an HDL simulator (e.g. Xcelium, VCS, Questa or open‑source tools such as Verilator or Icarus)
• Excellent problem‑solving skills and attention to detail

• Clear, structured communication in professional English—able to explain complex results concisely
• Collaborative and feedback‑oriented mindset
• Demonstrated ability to mentor and guide less experienced engineers
• Strong ownership, reliability, and follow‑through
• Curious, self‑motivated…