Analog & Mixed-Signal IC Layout Engineer

Engagement:
Contract; full-time also considered.

Full-time base salary: $160,000–$220,000 USD annually.

Contract compensation agreed separately.

Visibl Semiconductors (YC W26) builds custom silicon for power electronics. Many hardware companies could benefit from chips designed around their products, but the cost and complexity of custom development put them out of reach. We’re working to change that.

We’re looking for an Analog & Mixed-Signal IC Layout Engineer to turn reviewed circuit schematics into robust, verified physical designs for our power-electronics ASIC programs. You’ll work directly with our analog lead and the engineers responsible for integration and release, owning clearly scoped layout blocks and their verification handoff.

The work calls for more than closing a rule deck. You should understand how placement, routing, matching and parasitics affect circuit behavior, and resolve layout tradeoffs with the circuit designer before they become integration problems.

Layout planning and implementation. Work from the agreed schematic, PDK and electrical requirements to plan and implement analog and mixed-signal blocks. Translate matching, isolation, symmetry, current-density and sensitive-node requirements into placement and routing choices.

Parasitic-aware design. Collaborate with the analog lead on analog sensing blocks, voltage and current references, comparators, op-amps, bandgap references, DACs, low-noise sensing circuits, high-speed sensing paths, I/O-adjacent blocks, UVLO and support circuits as assigned. Use appropriate matching structures, guard rings, well isolation and shielding. Review extracted parasitics with the circuit designer and iterate the layout when they affect performance.

Physical verification. Run and debug design-rule checking (DRC), layout-versus-schematic (LVS) and parasitic extraction (PEX) using the project’s qualified tools and decks. Resolve errors and document any proposed exceptions for review; a clean tool run alone does not establish electrical performance.

Integration and handoff. Maintain the correct cells, hierarchy, pin interfaces and revision history. Support analog-on-top integration as scoped, and coordinate power routing, substrate/return domains and pad, ESD and clamp interfaces with the responsible engineers. Deliver layout sources, verified views, extraction outputs and a reproducible verification record for integration.

Own the layout and verification deliverables agreed for your assignment. Circuit architecture, digital RTL and final full-chip release approval remain with their named owners; top-level integration work is scoped explicitly.

• Hands-on ownership of analog or mixed-signal IC layout through tapeout. Be ready to explain your own blocks, verification responsibilities and what you learned from any resulting silicon validation.
• Practical experience with Cadence Virtuoso layout and the DRC, LVS and extraction flows used with a foundry PDK.
• Sound judgment around device matching, parasitic resistance and capacitance, isolation, guard rings, sensitive routing and current-carrying interconnect.
• The ability to read analog schematics, work with circuit designers and turn electrical constraints into a reviewable layout.
• A disciplined approach to verification debug, revision control and clear integration handoffs.
• The ability to work independently on a bounded assignment, communicate progress and raise missing requirements or schedule risks early.

Experience with multi-domain substrate integration, isolation and shielding across analog, digital and power blocks, protection structures, electromigration (EM) and IR-drop analysis is helpful. Power-management or gate-driver ICs, high-voltage/BCD processes, ESD…