FPGA Engineer; RTL) Cryptographic IP

We’re interested in engineers who can translate architectural requirements into robust RTL and support integration into FPGA or ASIC platforms.

• RTL development using Verilog or System Verilog.
• FPGA or ASIC design workflows.
• Simulation, verification and hardware debugging.
• Synthesis, timing analysis and optimisation.
• Integration with buses, memory systems and software interfaces.
• Experience balancing throughput, latency, area and power.

Cryptographic accelerators, secure boot, roots of trust and side-channel protection are particularly relevant.

PQC hardware experience would be valuable, alongside transferable experience implementing established cryptographic algorithms.

This posting is for the FPGA Engineer (RTL) Cryptographic IP role at Darwin Recruitment, based in United States.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.