Senior Logic Design Engineer; FPGA/ASIC)
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Engineering
Job Description & How to Apply Below
Locations:
Ukraine, Poland, Czech Republic, Romania, Slovakia, Spain
We are recruiting a Senior Logic Design Engineer to develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology.
This hands-on R&D role involves designing configurable, low-latency hardware and collaborating with architects, verification engineers and software specialists.
DCV.CK.JO.28.10.2026
Responsibilities
Design and implement complex System Verilog RTL modules.
Develop signal processing, waveform generation and real-time control logic.
Contribute to architecture, microarchitecture and RTL integration.
Perform synthesis, static timing analysis and optimization.
Debug and verify RTL functionality with verification teams.
Integrate digital IP and hardware-software interfaces.
Requirements
4+ years of professional FPGA/ASIC digital logic design experience.
Strong hands-on System Verilog RTL development.
Solid understanding of digital microarchitecture and synchronous design.
Experience with synthesis, STA, timing optimization and CDC.
Practical FPGA/ASIC implementation and RTL debugging experience.
Confident English (B2+).
Advantages: AMD/Xilinx Versal, Vivado, Questa/VCS, DSP, high-speed interfaces, ASIC IP, Python/Tcl automation and hardware-software co-design.
Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
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