PDK Testsite Engineer

Remote

6 months

• Design and develop semiconductor testsites, test chips, and device-level structures for process technology characterization and Process Design Kit (PDK) development.
• Create and modify physical layouts using Cadence Virtuoso or comparable electronic design automation (EDA) tools.
• Translate process characterization and device modeling requirements into test structures and silicon-ready layouts.
• Interpret semiconductor design rules, technology ground rules, and layout specifications.
• Perform and debug physical verification, including Design Rule Checking (DRC) and Layout Versus Schematic (LVS).
• Support testsite development through design, verification, tapeout preparation, and silicon characterization.
• Analyze electrical measurement and silicon test results to identify device, interconnect, process, and design issues.
• Support the development and validation of PDK components, including device definitions, parameterized cells (PCells), technology files, models, and verification flows.
• Develop and maintain scripts to automate testsite generation, layout, verification, and data-processing workflows.
• Troubleshoot layout, PDK, physical verification, and EDA tool issues.
• Document testsite designs, verification methodologies, results, and engineering findings.
• Collaborate with process development, device modeling, design enablement, layout, CAD/EDA, test, and manufacturing teams.

• Proficiency with Cadence Virtuoso or similar integrated circuit design and physical layout tools.
• Understanding of semiconductor devices, fabrication processes, physical layout, and technology characterization.
• Knowledge of semiconductor design rules, DRC/LVS, and physical verification methodologies.
• Ability to translate technology specifications and characterization requirements into functional test structures.
• Strong analytical, troubleshooting, debugging, and problem-solving skills.
• Ability to interpret electrical measurement results and support silicon-level analysis.
• Experience with PDK development, validation, or related semiconductor design enablement activities.
• Strong technical documentation and cross-functional communication skills.

• Experience developing semiconductor test structures, testsites, test chips, physical layouts, or PDK components.
• Experience using Cadence Virtuoso or comparable IC design and layout tools.
• Experience with semiconductor design rule implementation and physical verification.
• Preferred experience with Cadence SKILL programming, Python, Tcl, or similar scripting languages.
• Preferred experience developing PCells, layout automation, or verification workflows.
• Familiarity with Synopsys IC Validator (ICV), Siemens Calibre, or comparable physical verification tools is a plus.
• Experience with PDK development and validation, advanced semiconductor technology nodes, device characterization, or electrical measurement techniques is preferred.
• Experience supporting test structures or test chips through design verification and tapeout is an advantage.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, Physics, or a related technical discipline, or equivalent relevant experience.

Excellent verbal and written English communication skills and the ability to interact professionally with a diverse group are required.

The expected base salary for this position ranges from $72.00 to $74.00/hour. Salary offers are based on a wide range of factors including relevant skills, training, experience, education, market factors, and where applicable, licensure or certifications obtained. In addition to salary, a competitive benefit package is also offered.

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