Senior PCB Layout Engineer

This role focuses on owning the high-speed printed circuit board layout for an Intel-based compute platform, taking complex designs from schematic handoff through fabrication release using Cadence Allegro. You will collaborate closely with hardware, signal integrity, mechanical, and manufacturing teams to deliver robust, manufacturable, high-density boards that meet demanding performance, reliability, and quality requirements.

• Lead the placement, stackup definition, routing, and release of complex, high-density, high-speed printed circuit boards using Cadence Allegro.
• Implement and verify high-speed interfaces, including DDR5/LPDDR5 and PCIe Gen4/Gen5, to meet design-rule and signal integrity requirements.
• Partner with hardware and signal integrity/power integrity engineers to develop constraints, perform pre- and post-layout simulations, and design power delivery networks.
• Define PCB stackups and material selections in collaboration with fabrication vendors, balancing performance, cost, reliability, and long-term availability.
• Manage BGA fanout and breakout strategies, including via-in-pad, blind and buried vias, and HDI techniques.
• Create and maintain PCB library footprints and padstacks to IPC-7351 standards in coordination with the component library process.
• Produce complete manufacturing documentation packages, including Gerber/ODB++ files, drill files, assembly drawings, fabrication notes, and support DFM, DFA, and DFT reviews with fabricators and contract assemblers.
• Support board bring-up, debug, and respin activities through structured design change control and revision management.
• Maintain accurate design archives and documentation in alignment with ISO 9001 and related quality system requirements.
• Contribute to the development and refinement of layout standards, design guidelines, and best practices for the engineering team.

• At least 8+ years of professional PCB layout experience, including a minimum of 2+ years of proficiency with current versions of Cadence Allegro PCB Editor.
• Demonstrated experience laying out high-performance processor platforms with BGA packages and multi-gigabit interfaces.
• Strong working knowledge of high-speed design principles, including impedance control, length and skew matching, differential pair routing, return path management, and crosstalk mitigation.
• Experience with constraint-driven design using Allegro Constraint Manager.
• Working knowledge of relevant IPC standards and their application in PCB layout and fabrication.
• Proven ability to deliver complete, manufacturable release packages and work directly with PCB fabricators and contract assemblers.
• Solid understanding of power integrity and thermal considerations as they relate to PCB layout.
• Associate's or bachelor's degree in electrical or electronics engineering technology, or equivalent practical experience.
• Hands-on experience with Cadence Allegro for layout design of complex PCBs, including HDI boards.
• Experience supporting board bring-up and debug activities in collaboration with cross-functional engineering teams.

• Experience implementing and verifying USB, Display Port/HDMI, and Ethernet interfaces to meet design-rule and signal integrity requirements.
• Experience with HDI technology, high-layer-count boards (12+ layers), and advanced stackup design.
• Background in designing for defense, aerospace, or other high-reliability applications, including familiarity with rugged design practices such as shock, vibration, thermal management, and conformal coating, as well as IPC Class 3 requirements.
• Familiarity with DO-160, MIL-STD-810, and MIL-STD-461 design considerations and related…