Mask Layout Designer

I'm working with an early-stage semiconductor company developing next-generation AI inference hardware
, using novel transistor-level circuits to improve computational efficiency.

They're looking for a Mask Layout Designer with experience in custom IC layout, physical verification and silicon tapeouts.

• Design custom transistor-level layouts from schematic through tapeout.
• Develop tight-pitch standard cells, circuit blocks and ESD/I/O structures.
• Own full-chip integration, DRC/LVS sign-off and physical verification.
• Collaborate with circuit designers to optimise performance and layout efficiency.

• Proven experience in custom IC layout and multiple silicon tapeouts
  .
• Strong proficiency with Cadence Virtuoso and Calibre or IC Validator
  .
• Experience with full-chip DRC/LVS sign-off.
• Knowledge of matching, parasitics and tight-pitch layouts.
• Experience with 28nm or similar process nodes
  ; SKILL scripting advantageous.

• Join an early-stage company developing fundamentally new AI computing hardware.
• Work directly with experienced chip architects, with ownership from custom cells through tapeout.
• Contribute to novel circuit designs shaping the future of AI inference.

Remote | Initial 9-month contract, with potential extension.