SerDes Validation Engineer

Own hands-on implementation and post-silicon validation of high-speed Ser Des links, including 112G and 224G PAM
4. The work spans IP configuration, equalization tuning, lab characterization, and debugging across physical channels and system components, in close partnership with signal integrity, hardware, and firmware teams.

• Integrate and configure Ser Des IP blocks in custom hardware, including register-level setup.
• Tune CTLE, FFE, and DFE settings to improve eye margin and reduce bit error rates across board, cable, and backplane channels.
• Bring up, characterize, and debug high-speed PAM4 links after silicon is available.
• Use oscilloscopes, BERTs, pattern generators, and protocol analyzers to measure performance and isolate faults.
• Correlate lab measurements with channel models, layout, and simulation alongside SI/PI engineers.
• Build Python-based lab automation and support firmware-driven monitoring and validation flows.

• Hands-on experience bringing up and validating 56G, 112G, or 224G PAM4 links, or PCIe Gen5/Gen6 interfaces.
• Practical knowledge of Ser Des implementation, configuration, equalization, and physical-layer debugging.
• Understanding of TX/RX equalization and how channel behavior affects link performance.
• Experience with lab measurement, characterization, and scripting, preferably in Python.
• Ability to trace complex issues across silicon, boards, cables, firmware, and system behavior.
• Strong collaboration skills across hardware, firmware, SI/PI, and systems teams.

• Experience with PAM4 links in data center, networking, accelerator, switch, or high-performance computing systems.
• Familiarity with Ethernet, PCIe, CXL, or similar high-speed protocols.
• Experience with commercial or in-house Ser Des IP, channel modeling, compliance testing, or production validation.