Lead STA Engineer

A Lead STA Engineer role driving static timing analysis and methodology for an ultra-low-power general-purpose processor. The position is part of a newly formed hardware engineering group and focuses on timing convergence across IP, subsystem, and SoC blocks built in advanced finFET technologies.

• Develop and drive timing flows and methodology from scratch in Cadence Tempus or Synopsys Primetime for advanced finFET and multi-patterning processes
• Own timing convergence across IP, subsystem, and SoC-level blocks
• Define timing margining, PVT/RC corners, extraction methodology, and sign-off correlation with synthesis and place-and-route
• Develop slew rate, glitch, and noise checks to ensure robust design quality
• Build custom timing checks specific to the proprietary ultra-low-power architecture
• Partner with RTL, DFT, and IP vendors to define and drive SDC constraints
• Collaborate with the post-silicon bring-up team to ensure strong pre-silicon to post-silicon timing correlation

• Master's degree in Electrical Engineering with 5+ years of industry experience, or PhD in Electrical Engineering with 3+ years of industry experience
• Proven track record delivering IP, subsystem, or SoC STA sign-off across multiple tape-outs at 12nm or below
• Hands-on experience with Cadence, Synopsys, or Mentor EDA flows for STA and simulation, including hierarchical design and abstraction techniques
• Experience converging timing on high-frequency and low-power designs
• Expert knowledge of static timing analysis, constraints and exceptions, corner and voltage definitions, and timing margining
• Strong scripting skills in TCL, shell, and Python

• Knowledge of computer architecture, physical design, or ASIC implementation
• Experience with full-chip sign-off budgeting and CAD flow infrastructure for PD engineers
• Familiarity with circuit design, device physics, deep sub-micron technology, and SOI
• Experience integrating analog or mixed-signal macros at the top level

• Base salary generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits
• 401K match, company-paid benefits, equity program, paid parental leave, and flexibility for personal and professional development