HBM Design Engineering Lead - MTS​/SMTS​/DMTS

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) is a division within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications. Using TSV (Through Silicon Via), we stack multiple DRAM chips on a high-speed memory controller with an integrated logic chip in one package, significantly increasing memory density and bandwidth through parallelization. Our designs leverage both custom digital and RTL2

GDS flows, and our ultimate goal is to deliver the lowest power per bit solutions in the industry.

You will help shape next-generation High Bandwidth Memory solutions for artificial intelligence and accelerated computing. You will serve as a senior technical contributor and technical project leader, guiding work from architecture definition through silicon bring-up and post-silicon support. You will partner across design, process, packaging, and product teams to deliver reliable silicon with broad business impact. You will influence future memory architectures while mentoring engineers and improving design execution.

• Own and deliver critical High Bandwidth Memory (HBM) design blocks and subsystems from architectural definition through schematic, implementation, verification, tape‑out, and post‑silicon debug.
• Drive robust, high‑performance designs by balancing performance, power, reliability, yield, and manufacturability trade‑offs.
• Lead root‑cause analysis and resolution of complex pre‑silicon and post‑silicon issues across circuit design, architecture, process integration, and packaging interactions.
• Serve as technical project lead for one or more HBM programs, coordinating execution across architecture, layout, verification, validation, process integration, packaging, test, and product engineering teams.
• Define and communicate technical strategy, priorities, and execution plans while proactively identifying risks, dependencies, and schedule impacts.
• Research, develop, and influence next‑generation HBM architectures aligned with artificial intelligence, machine learning, and high‑performance computing workloads.
• Apply deep knowledge of Dynamic Random‑Access Memory (DRAM) operation, Joint Electron Device Engineering Council (JEDEC) specifications, memory subsystems, and high‑speed interfaces to architect scalable, future‑ready solutions.
• Mentor engineers through design reviews, architectural guidance, and hands‑on problem‑solving while driving improved design methods, guidelines, and execution discipline across HBM programs.

• 15+ years of experience in DRAM, HBM, advanced memory, system‑on‑chip, or application‑specific integrated circuit design roles.
• Proven experience delivering complex designs from architecture through silicon bring‑up and post‑silicon debug.
• Strong expertise in DRAM operation and JEDEC standards, preferably including HBM product families.
• Extensive experience with complementary metal‑oxide‑semiconductor circuit design, transistor‑level design, and semiconductor device physics.
• Demonstrated technical project leadership across multidisciplinary engineering teams.

• Experience with digital design using Register Transfer Level methodologies such as Verilog, or similar.
• Experience with analog modeling and simulation tools such as Fast Spice, HSPICE, or similar.
• Deep technical expertise in one or more areas such as DRAM memory array design,…