Principal Modem SOC Design Engineer - Terawave

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based connectivity with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations. As a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team, you will be a technical design leader for the Tera Wave satellite communication System on Chip (SOC).

This individual contributor role carries technical leadership scope. You will lead RTL design for the modem SOC and its subsystems, define microarchitecture from communication system specifications, and drive integration across the modem PHY, Arm compute, debug, and IO infrastructure. As the technical interface among the system architecture, SOC architecture, software architecture, performance modeling, and FPGA prototyping teams, you will align design decisions from specification through production silicon.

• Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems
• Define microarchitecture based on satellite communication system specifications and performance requirements
• Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration
• Integrate debug subsystem components using Arm Core Sight architecture and associated trace infrastructure
• Drive subsystem and SOC-level integration, including clock, reset, and general-purpose IO (GPIO) subsystems
• Serve as the technical interface to the system architecture, SOC architecture, and software architecture teams
• Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
• 12+ years of experience in digital ASIC or SOC RTL design
• Experience defining microarchitecture for modem or communication SOC blocks from system specifications
• Experience with Arm compute subsystem design, including AXI interconnect and SRAM controllers
• Experience with LPDDR4, LPDDR5, LPDDR6, or other high-speed memory interface subsystems
• Experience with high-speed Gigabit Ethernet interface subsystems
• Experience with SOC-level integration, including bus fabric, clock, and reset architecture
• Experience with debug subsystem design using Arm Core Sight components
• Experience with synthesis, timing constraint development, and timing closure support

• Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
• Experience with RTL design in Verilog or System Verilog for modem datapath or PHY IP blocks
• Experience with signal processing hardware such as filters, FFTs, equalizers, or forward error correction (FEC)

For CA applicants is $ - $. For WA applicants is $ - $. Other site ranges may differ.

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past…