Mixed Signal Design Verification Engineer

The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.

The Opportunity Allegro Micro Systems is seeking an enthusiastic and motivated Mixed‑Signal Design Verification (MSDV) Engineer to join our development team. In this role, you will work under the guidance of senior technical leads to develop and execute top-level mixed‑signal verification test benches for our market‑leading automotive and industrial integrated circuits. You will act as a key interface between transistor‑level analog building blocks and digital control systems, running functional simulations across power sequencing, register configurations, and system‑level testcases to ensure first‑pass silicon success.

Run and debug top‑level AMS simulations using Cadence AMS Designer and Virtuoso to verify chip‑level interactions between analog front‑ends and digital logic. Assist in writing and maintaining behavioral models and test benches using Verilog, System Verilog, and Verilog‑AMS/Real‑Number Modeling (RNM/wreal). Verify power‑up/power‑down sequences, brown‑out events, and reset circuitry (POR, POK, UVLO) across voltage and temperature corners to ensure proper start‑up behavior. Validate register maps, EEPROM configuration loads, read/write protocols, and trim test modes against design specifications.

Log and track verification bugs using Git Lab issue tracking, applying standard workflow states (Analysis Pending, Verified) to support tapeout readiness. Partner with Analog Design, Digital Design, and Systems Engineering to review coverage metrics in Jama Connect and support testcase closure.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. 1–3 years of industry or relevant academic/internship experience in mixed‑signal design verification or IC design. Familiarity with Cadence EDA tools (Virtuoso, ADE Explorer/Assembler, AMS Designer). Understanding of HDL languages (Verilog, System Verilog) and introductory knowledge of Verilog‑A/AMS. Solid grasp of fundamental analog circuits (amplifiers, bandgaps, LDOs, ADCs, oscillators) and digital logic basics.

Basic familiarity with Linux environments and scripting (Python, Bash, or Skill) is a plus. Exposure to issue‑tracking tools (e.g., Git Lab) and requirements management systems (e.g., Jama Connect). Curious, proactive problem‑solver with strong written and verbal communication skills who enjoys learning and collaborating in a global engineering environment.

Join Allegro and become part of a team where your contributions truly matter. We foster a culture of Real Innovation, empowering you to push boundaries, develop cutting‑edge solutions, and drive continuous improvement. Your work will create a Real Impact by solving complex real‑world challenges that fuel our success and shape the future of technology. You’ll experience Real Connection, collaborating with talented colleagues around the globe in an environment built on trust, respect, and a shared purpose.

Join us—and help build what’s next. At Allegro, we are committed to providing a harassment‑free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status,…