Senior Verification Engineer - Media IP

Job Overview:

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the Arm Systems Media IP team! The team is responsible for the development of Image Signal Processors (ISPs), Display Processors, and Video codecs for deploying within Arm Compute Subsystems for various end markets, including automotive, IoT, and client market segments. Our intellectual property encompasses RTL, reference drivers, tools, and libraries, enabling our customers to build upon our work to create innovative products!

• Own and drive verification for a DPU subsystem comprising multiple units, or for a particularly complex DPU unit, from early planning through sign-off.
• Contribute to the overall DPU verification architecture, planning, integration strategy and quality criteria.
• Architect reusable, scalable and high-performance System Verilog/UVM environments and verification IP.
• Define verification plans, coverage models, sign-off criteria and measurable quality goals for the owned verification scope.
• Identify technical and schedule risks early, establish mitigation plans and drive them to resolution across teams.
• Review proposed architecture and design changes for correctness, observability, testability, performance and verification complexity.
• Lead the resolution of complex unit-level, cross-unit, integration or system-level failures.
• Align verification activities and dependencies across the relevant unit, subsystem and DPU teams.
• Drive improvements in verification methodology, automation, reuse, regression efficiency, debug and continuous integration.
• Use verification data to identify quality gaps, improve bug discovery and guide engineering priorities.
• Influence project planning and technical decisions through clear, evidence-based recommendations.
• Build effective links with architecture, design, software and other Arm engineering teams to ensure that the DPU integrates successfully into complete systems.

• Strong knowledge of, and extensive hands-on coding experience with, System Verilog and UVM, including the architecture, implementation and review of complex verification environments.
• Hands-on verification experience in standard on-chip bus protocols such as AMBA APB and AXI, or other industry-standard protocols.
• Demonstrated experience developing verification plans from scratch for complex IP or subsystems, including verification strategy, stimulus, checking, coverage, risk assessment and sign-off criteria.
• Experience owning verification of a subsystem comprising multiple units, or of a particularly complex unit.
• Experience developing verification test benches.
• Hands-on programming experience using Python, C or another standard programming language.
• Knowledge of the tools and infrastructure that support effective verification workflows, such as regression setup and triage, version control and linting.

• Experience with power-aware verification.
• Experience with formal verification.
• Experience working at IP or subsystem level.
• Contributions to the domain through conferences or technical papers.
• Experience with performance analysis.
• Experience working with reference models developed in
  
  C.

• Ability to provide clarity and direction while working through ambiguity and evolving specifications.
• Ability to engage and align stakeholders to clarify requirements and resolve issues.
• Willingness to take ownership where needed and drive cross-team work to completion.
• Clear communication and a collaborative approach to technical leadership.

Please note that no relocation package is available for this role.

If skilled worker sponsorship is required, Arm will meet costs associated with sponsorship for the employer only. All fees associated with the individual’s application e.g. visa application fee and Immigration Health Surcharge, will be the responsibility of the successful candidate.

At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email  To note, by sending us the requested…