Design Verification Engineer

Design Verification Engineer

Location:

Cedar Rapids, IA Job : #73264 Pay Range: $68-79 ph (W2) Duration: 6 mos Avionics FPGA/ASIC organization focused on delivering high performance, safety critical digital hardware for company products. This role is ideal for a highly experienced and motivated Electrical or Computer Engineer with a strong background in design verification for complex ASIC, FPGA, and SoPC developments. As a Design Verification Engineer, you will apply industry leading verification methodologies to ensure robust, compliant, and high quality airborne electronic hardware used across our next generation Displays, Computing, and Networking solutions.

You will work closely with digital designers, systems engineers, and certification teams to drive requirements based and coverage driven verification from concept through integration and certification under DO 254 DAL

A.
* Develop verification plans based on requirements capture, decomposition, and traceability.
* Architect and implement advanced constrained random and directed verification environments (UVM/System Verilog).
* Create, develop, and maintain reusable verification components, test benches, sequences, and functional coverage models.
* Perform ASIC/FPGA/SoPC verification using simulation, inspection, analysis, and hardware test methods.
* Conduct functional, code, and assertion coverage analysis and drive closure against verification goals.
* Apply best practice verification techniques including linting, CDC analysis, LEC, assertions, and regression automation.
* Collaborate with design teams to review architecture, interface specifications, and RTL implementation for testability and completeness.
* Generate DO 254 DAL A verification artifacts and support certification activities for Airborne Electronic Hardware (AEH).
* Participate in technical peer reviews and FAA SOI audits.
* Contribute to engineering bids, support RFIs/RFPs, and provide accurate estimation for verification scope and effort.
* Communicate effectively across engineering, program management, and customer teams.
* Mentor junior verification engineers and recommend workflow/tool enhancements for continuous improvement.
* May perform responsibilities associated with project engineering as required.

Qualifications:

* Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field
* Experience developing test benches and verification environments in System Verilog, VHDL, and/or Verilog.
* Hands-on experience with verification and simulation tools (e.g., Questasim, Vivado, Libero, Synplify Pro).
* Understanding of common digital interfaces (PCIe, DDR, Ethernet, I2C, ARINC
429, CAN, etc.).
* Experience verifying timing behavior, device level timing constraints, and clock domain crossings.
* Experience with scripting languages such as Python, Perl, Linux shell, or C/C++.
* Ability to work independently and collaboratively with globally distributed, cross functional engineering teams. Prefer:
* Strong experience with UVM and constrained random verification methodology.
* Knowledge of DO 254 processes and verification-related design assurance activities.
* Familiarity with chip level verification best practices including functional coverage, code coverage, assertions, and LEC.
* Experience with video or networking technologies.
* Demonstrated ability to manage cost, schedule, and performance for verification activities.
* Basic risk management experience including identification, quantification, and mitigation planning. Benefits provided: 401K, medical, dental, and vision, sick time as applicable to state law Butler America Aerospace, LLC. is an equal opportunity employer. Butler evaluates applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information and other legally protected characteristics. The Butler America Aerospace, LLC.

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