Memory PHY RTL Design Engineer

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We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence while being direct, humble, collaborative and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high‑speed LPDDR, DDR IPs. You will be part of the definition, design and development phase of industry‑leading Memory PHYs and interface IP. This opportunity includes creating new IO designs and working on multiple designs while enhancing methodologies in parallel.

You have a passion for modern, complex processor architecture, digital design and verification in general. You are a team player with excellent communication skills. You possess strong analytical and problem‑solving skills and are willing to learn and ready to take on challenges.

• Microarchitectural design and RTL implementation of IP features.
• Synthesis, STA, CDC/RDC, UPF design/simulation, power optimization and gate simulation.
• PHY digital architecture development from pathfinding, coding, verification to physical implementation.
• Collaborate with the Firmware team to develop firmware sequences and algorithms.
• Analyze RTL design for power and timing optimization.
• Collaborate with the Design Verification team to drive timing synthesis and physical implementation.
• Participate in design specification and RTL code reviews.

• Digital design engineering experience.
• Excellent knowledge of Verilog, System Verilog, C and a scripting language; experience with Python, Perl and TCL is a plus.
• Proficient in debugging firmware and RTL code using simulation tools.
• Experience with UVM test benches and working in Linux and Windows environments.
• Knowledge of clocking architectures, synchronization and CDC methodology.
• Experience with SERDES, DDR, Memory Controller or MAC design is preferred.
• Strong understanding of computer organization/architecture.
• Mixed signal RTL experience is a plus.
• Exposure to leadership or mentorship is an asset.

• Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.

Markham, Vancouver

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.