RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

We are seeking an RTL Design Engineer to join our Security IP (SECIP) team, where we design and verify embedded microprocessor subsystems and hardware accelerators that enhance performance and functionality. These subsystem IPs deliver high-performance capabilities to System-on-Chip (SoC) products across AMD business units, including client computing, servers, graphics, and gaming. In this role, you will contribute to RTL design and subsystem integration for a variety of embedded microprocessor subsystems.

Your work will support areas such as security policy management, cryptography, data compression, power management, and other advanced applications. THE PERSON:
An experienced hardware RTL design engineer with a proven ability to deliver block-level IP and/or MP subsystem designs and associated verification tasks. Someone who proactively seeks to improve workflows, identifies and resolves technical challenges, and collaborates effectively with team members. Demonstrates clear communication, problem-solving skills, attention to detail, and the ability to work well in diverse, team-oriented environments.

KEY RESPONSIBILITIES:

Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics) Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules) Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

PREFERRED EXPERIENCE:

Proven understanding of CPU and MP subsystem architecture, Datapath accelerator RTL microarchitecture, as well as FPGA based simulation or emulation methodology Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile) Excellent knowledge of state-of-the-art RTL design and verification methodology and best practices, and C-DPI test design Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.

ACADEMIC CREDNTIALS:
Bachelor's or master’s degree in electrical engineering, Computer Engineering, or Computer Science, or a related field #LI-DP1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy,…