Job Description & How to Apply Below
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are seeking a Front-End Silicon Design and Integration Engineer to join our Security IP team, where we design and verify embedded microprocessor subsystems, hardware accelerators, and other components that enhance system performance and functionality. These components support System-on-Chip (SoC) products across multiple business areas, including client computing, servers, graphics, and gaming. In this role, you will contribute to RTL (Register Transfer Level) design and synthesis, analyze performance, power, and area (PPA) to optimize design quality, and develop and automate design rule checks.
You will also perform equivalence and integration checks to ensure accuracy and reliability, while collaborating with cross-functional teams to integrate IP into larger SoC systems. Additionally, you will continuously learn and adopt new tools and methodologies to improve efficiency and innovation. We welcome candidates with strong problem-solving skills, attention to detail, and a willingness to learn—even if you don’t have experience with every tool or acronym listed.
If you are passionate about hardware design and eager to grow in a collaborative environment, we encourage you to apply. THE PERSON: A talented FEINT engineer with strong records of technical ownership and execution to conduct synthesis, PPA analysis, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members.
A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.
KEY RESPONSIBILITIES:
Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools
PREFERRED EXPERIENCE:
Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc. Proficient with Verilog, C/C++ and other scripting languages (e.g. TCL, Ruby, Perl, Python and Makefile) Excellent skills with Unix/Linux environment Familiar with RTL coding techniques for competitive PPA-measured QoR Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
Good understanding of gate level circuit design and physical level design concept and methodology Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments ACADEMIC CREDENTIALS:
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. #LI-DP1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment…
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