Job Description & How to Apply Below
We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP. This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.
Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces. THE PERSON:
Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills
KEY RESPONSIBILITIES:
Firmware design and development of DDR PHY & DRAM Training steps Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power Pre-silicon FW coding and simulation against Architectural and RTL models Post-silicon lab bring-up and optimization of DDR Init and Run Time FW Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin Working with SoC/Product firmware teams to define features and spec PREFERRED
SKILLS:
Excellent knowledge of C, C++ and any scripting language, such as Python. Good Knowledge of Verilog/System Verilog and digital simulation debug. Ability to adapt learn new toolsets and frameworks is required. Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plus Post-silicon experience developing firmware on real hardware is required.
Experience with SERDES, DDR, Memory Controller Design experience is preferred Strong understanding of computer organization/architecture. Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.
Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.) ACADEMIC CREDENTIALS:
Bachelor's degree in Electrical or Computer engineering is strongly desired. Master's or PhD degree is a plus.
LOCATION:
Markham, ON #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.
We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.
THE ROLE:
The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs. Be a part of the…
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