Job Description & How to Apply Below
As part of the Memory and Systems IP (MSIP) team, you will dive into different verification activities, focusing on System Verilog/UVM testbench development. Strong analytical skills and the ability to communicate effectively across time zones are crucial.
Your role will significantly impact project success through verification and automation.
Key Responsibilities:
• Create and enhance System Verilog/UVM-based test benches
• Work with architects and validation engineers for deep integration
• Develop staging and comprehensive test plans
• Effectively test designs to meet performance goals
• Drive automation improvements using Perl, Python, and Tcl/Tk
Requirements:
• Experienced in complex verification environments (System Verilog/C++)
• Strong knowledge of verification tests and assertions
• Exposure to relevant design verification tools (VCS, Debussy)
• Bachelor’s or Master’s degree in a relevant discipline
• Creative thinker and an adept problem solver
Drive innovation at AMD as you tackle complex verification challenges in Markham.
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