Senior Layout Engineer -Speed SerDes at Synopsys

Position: Senior Layout Engineer for High-Speed SerDes at Synopsys
Drive your career forward as a Senior Layout Engineer focusing on high-speed Ser Des race the opportunity to innovate and mentor in a dynamic engineering landscape.

As a key member of the High-Speed Mixed-Signal IP Layout Team at Synopsys, you will apply your specialized knowledge in analog and mixed-signal layout to enhance methodologies.

Your role will include defining detailed project scopes, mentoring junior engineers, and ensuring the highest quality in layout development. Collaborate effectively across various teams, translating technical challenges into strategic workflows and solutions.

Key Responsibilities:

• Define and manage layout effort and timelines

• Enhance Ser Des IP quality through innovation

• Collaborate with customers for technical specifications

• Utilize modern tools to refine layout processes

• Create essential documentation for workflows and deliverables

Requirements:

• Strong background in high-speed Ser Des layout

• Familiarity with multi-Gbps NRZ and PAM4 systems

• Hands-on debugging and problem-solving expertise

• Well-versed in Synopsys layout tools and verification software

• Understanding of advanced packaging solutions

Impact the semiconductor industry through your leadership and expertise with Synopsys, driving continuous improvement and excellence.
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