Job Description & How to Apply Below
As a senior member of the design team, you will lead the RTL design process for ASIC projects, ensuring high standards of quality and performance. Your extensive experience with Verilog, along with your background in networking protocols, will guide the design of next-generation solutions. Collaboration with various technical teams and mentoring junior designers will be crucial aspects of your role.
Key Responsibilities:
• Lead RTL design for complex networking applications
• Integrate AI tools for streamlined design processes
• Work with cross-functional teams on IP core specifications
• Ensure high verification quality metrics are met
• Mentor and guide less experienced engineers
Requirements:
• Deep knowledge of Verilog and ASIC design principles
• Extensive experience with EDA and synthesis tools
• Familiarity with networking and encryption protocols
• Proficiency in automation scripting languages
• Bachelor's or Master's in computer or electrical engineering
Utilize your RTL expertise to make a significant impact in networking innovation and design excellence.
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Position Requirements
10+ Years
work experience
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