Memory Subsystem; Shift Left Lead Job Markham area,Ontario Canada,Engineering

Position: Memory Subsystem (Shift Left) Lead

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THE ROLE:

The Memory Subsystem team is seeking a senior technical leader to guide DDR Subsystem Shift Left execution and SoC integration. This role focuses on enabling pre-silicon execution using production firmware and ensuring the DDR subsystem is prepared for SoC delivery and bring-up. You will help establish system-level direction, execution standards, and debug strategies, enabling DDR behavior to be exercised across configurations and integrated effectively into SoC environments.

This is a technical leadership role that combines hands-on contribution with mentoring and coordination, focused on supporting individual contributors and scaling DDR Shift Left capabilities into a sustainable, high-impact function.

THE PERSON:

You communicate complex technical concepts clearly and effectively to a variety of audiences through written, verbal, or visual means, including documentation, presentations, trainings, and technical discussions. You collaborate thoughtfully with engineers across experience levels, enjoy mentoring and knowledge sharing, and contribute to building an inclusive, supportive team environment.

KEY RESPONSIBILITIES:

Define product features and capabilities; contribute to architecture and micro-architecture requirements; help develop technical specifications for SoC and IP blocks; and provide technical guidance to execution teams

Understand the SoC as a complete system, including hardware (silicon), firmware, BIOS, and software, and work to ensure alignment across these components to enable features while optimizing performance and power

Work cross-functionally with IP and domain architects to identify and assess complex technical issues and risks, and collaborate on architectural approaches to meet product requirements

Share knowledge and contribute to Platform & System Architecture discussions and documentation

As a primary technical steward, support architecture analysis and technical solutions related to feature updates and change requests

Collaborate closely with Design teams on area and floorplan considerations, verification test plan reviews, timing targets, emulation plans, pre-silicon issue resolution, and performance and power verification signoffs

Partner with post-silicon teams to support debug and resolution of product performance, power, and functional issues

PREFERRED EXPERIENCE:

Strong foundation in Systems and SoC architecture, with experience in one or more of the following areas: CPU or GPU, memory subsystems, fabrics, CPU/GPU coherency, multimedia, I/O subsystems, clocks, resets, virtualization, or security

Experience analyzing CPU-, GPU-, or system-level micro-architectural features to understand performance characteristics across workloads

Experience with power management microarchitecture, low-power design, and power optimization, including awareness of power impact at the architecture, logic design, and circuit levels

Clear, effective communication and collaboration skills, including the ability to work across disciplines and experience levels

Comfort collaborating with architects and engineering partners across teams and geographies, with an inclusive and respectful working style

ACADEMIC CREDENTIALS:

Bachelor’s or master’s degree in computer engineering, Electrical Engineering, or equivalent practical experience

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