Senior Engineer, Analog Layout and Methodologies

Join Synopsys as a Senior Engineer specializing in Analog Layout and Methodologies. Utilize your custom layout skills to streamline design processes and improve silicon reliability.

This role demands a strong background in analog mixed signal layout, particularly in device matching and EMIR. You will lead the charge in top-down macro floor planning, collaborating with circuit designers and engaging in thorough verification processes. Expect to document improvements and facilitate global teamwork to elevate project standards.

Key Responsibilities:

• Optimize mixed signal layouts with a focus on device matching

• Lead macro floor planning and drive layout execution

• Conduct extensive DRC, LVS, Antenna, and DFM checks

• Proactively manage ESD and latch-up verification

• Automate layout tasks with scripting skills for improved efficiency

Requirements:

• Bachelor’s or Master’s in Electrical Engineering or similar

• 5+ years of relevant layout design experience

• Mastery of Custom Compiler SDL or Virtuoso XL

• Familiarity with various verification techniques

• Scripting expertise in TCL, Perl, or Python is a bonus

Impact silicon yield and reliability by delivering top-notch layouts that minimize surprises and streamline processes at Synopsys.
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