Senior Physical Design Engineer

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The DXIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.

As a seasoned Physical Design engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent opportunity for robust individuals looking to make a difference.

• Drive all implementation aspects of next generation of IPs, including multiple I/O protocols such as PCIe, UCIe, UALink & Infinity Fabric link‑layer.
• Own implementation activities:
  Synthesis, floorplan, placement, clock tree synthesis, routing, and STA closure for high‑speed (>2G) designs with complex clocking infrastructures.
• Work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, developing reference floor plans, implementation scripts for SoCs worldwide, and supporting SoCs worldwide.

• Synthesis, floor‑planning, placement, clock tree synthesis, post‑route timing closure for high‑speed >=2GHz designs.
• Experience with STA, the physical design flow and scripting in TCL, Python.
• Fusion Compiler experience (preferred).

• Bachelors or Masters degree in Computer Engineering, Electrical Engineering, or related field.

Location:

Markham, Vancouver, Ottawa.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.