Job Description & How to Apply Below
This role within AMD's S3 organization entails working closely with the Physical Design integration team to develop and optimize full-chip floor plans from RTL. You will utilize your comprehensive experience in physical design to drive early implementation decisions, focusing on high-quality results in complex environments. Your expertise will be instrumental in defining and refining chip-level structures.
Key Responsibilities:
• Master full-chip floorplan design and integration
• Translate RTL into strategic chip structures
• Innovate pin and bus topology planning
• Perform feasibility analysis for design decisions
• Engage with RTL and architecture teams for seamless execution
Requirements:
• Proven expertise in SoC physical design and tapeouts
• Strong focus on floor planning and design optimization
• Hands-on experience with relevant design tools
• Proficiency in automation scripting (Tcl, Perl, Python)
• Degree in electrical or computer engineering is preferred
Seize the opportunity to enhance your physical design skills and contribute to AMD's mission in revolutionizing technology.
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