SoC Debug Engineer

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm's Silicon Validation team is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers. We are currently seeking a Senior candidate for the position to perform of SoC Debug Engineer for Server/Compute/Mobile chipsets.

• Lead Bring up, debug, analyze failures at the embedded platform level in both pre-Si and post-Si phase
• RTL inspection and dive in required to root cause pre-si debug and JTAG and Si exposure to root cause post-si issues
• Lead on initiatives for faster debug at the platform level including isolating failing components of a system
• Creating and leading debug strategies and plans for partners to more rapidly triage failures to isolate specific components including PVT and marginality issues.
• Perform real-time debugging and troubleshooting of server hardware, including motherboards, processors, memory, storage devices, power supplies, and networking components.
• Investigate manufacturing defects, determine root causes, and implement corrective actions to improve product quality and reliability

• 6+ years of experience with pre-si and post-silicon enabling, bring-up , analyze failures at the embedded platform level
• RTL inspection and understanding of basic RTL
• Need to have experience solving ample of complex debug in pre-si and post-si phases
• Lead the effort for develop and implement solutions for faster debug at the platform level including isolating failing components of a system
• Creating debug strategies and plans for partners to more rapidly triage failures to isolate specific components including PVT and marginality issues
• Sys Debug lead roles to drive complex issues to Root-Cause
• Debugging low level software and hardware issues
• Debug tools including JTAG
• Using Lab Equipment (Logic Analyzer, Scope, Signal Generator etc…)

• Strong programming and scripting languages (C, Assembly, Perl, Python, etc.)
• Good understanding of power and performance
• Strong Knowledge of TCU, PVT, Fmax, Vmin test methodology and hands-on experience
• CPU and SoC architectures for Server/Compute/Mobile chipsets.
• Hands on experience in handling server specific use-cases including Server Boot Configuration and Server Reset Scenarios.
• Debug experience of Server Reboot stress scenarios including both Cold and Warm boot.
• Knowledge of multi-die secure boot flow and debugs involved in multi-die configuration

Required:

Master's, Computer Engineering and/or Electrical Engineering

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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