RTL Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whether you’redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward.

Join us and, together, we’ll advance your career.

This role is an excellent opportunity to work on the cutting-edge next generation technologies that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. You will join one of the fastest-growing field of Chiplet Interconnect technology rapidly being adopted across the VLSI industry. The team works on supporting both AMD proprietary I/O protocols and is also a key driver for industry standard

Universal Chiplet Interconnect Express (UCIe) and Ultra Accelerator Link (UALink). The IP portfolio caters to short/ultra-short reach die-2-die interconnect with different bounding boxes tied to beachfront, Power, BER requirements. As a member of this team, you get a chance to work on IP development, drive design-specification, work on digital design and collaborate in the whole spectrum of areas include DFT, Firmware, Design verification, and Physical Design.

Enjoys being in an environment where they can grow and learn with sense of team spirit.

Strong analytical thinking and problem-solving skills, excellent attention to detail. Eager to learn new designs and implementation techniques. Must have good collaboration and interpersonal skills. Excellent communication skills with leadership qualities.

• Experience with I/O protocols like USB, PCIe, CXL.
• Experience in developing micro-architecture for any given module.
• RTL design experience with multi-clock, high frequency designs, low latency, low power & high performance.
• Debugging/Post Silicon Bring up
• Good Documentation and presentation skills.
• Micro-architecture of simple to complex digital blocks.
• RTL development using best industry practices.
• Optimize design for key metrics like Area, Power, Performance etc.
• Ability to work with cross-functional teams like DFT, Implementation, Verification, Emulation, Firmware regularly.

• Experience in digital front-end implementation, including micro-arch. definition
• Experience with scripting/automation languages like Python/Perl
• Firmware on Hardware-Firmware co-design
• Experience with state-of-the-art industry standard digital tools
• Preferred experience in design with multiple clock domains
• RTL design experience with multi-clock, high frequency designs
• Knowledge in digital RTL Digital Design and Implementation
• Experience with Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)

• Bachelors or Masters degree in electrical engineering or equivalent preferred.

Markham, ON

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.