Senior FPGA IP Solutions Engineer – Robotics Technology

Altera is seeking a talented Senior FPGA IP Solutions Engineer to join the Robotics Technology Group in Marlow, UK. This hands‑on role focuses on the design, verification, and delivery of high-performance FPGA IP and solutions that enable next-generation robotics and industrial automation systems.

Working within a small, highly technical team, you will develop reusable RTL IP for sensor ingestion, data pre‑processing, fusion pipelines, and real‑time compute accelerators for robotics use cases. Your primary ownership is the RTL IP and the low‑level software interface (HAL / driver API) that exposes it—covering micro‑architecture, RTL implementation, simulation, timing closure, and Quartus Prime / Platform Designer integration. You will also maintain a clear awareness of how that IP fits into the broader system and solution stack, collaborating with software and systems engineers on reference designs and customer‑facing robotics platforms.

This role emphasizes deep FPGA IP and HAL craftsmanship—high‑performance RTL, verification and simulation, and clean low‑level APIs—while requiring enough system‑level awareness to integrate cleanly into end‑to‑end robotics solutions.

• - Design, implement, and optimize high-performance soft IP in Verilog/System Verilog for robotics and industrial solutions
• - Define and maintain low-level HAL / driver APIs that expose IP capabilities to embedded and host software
• - Develop RTL for sensor ingestion, pre-processing, fusion, and mathematical / DSP algorithms mapped efficiently to FPGA fabric
• - Apply strong FPGA architecture awareness to drive resource allocation (ALMs, DSP, memory), Fmax, and power/performance trade‑offs
• - Integrate IP into system designs using Quartus Prime and Platform Designer (Avalon / AXI interconnects, streaming and memory‑mapped fabrics), with awareness of full‑stack solution integration

• - Write and maintain test benches; perform functional simulation and regression of IP and subsystems
• - Drive static timing analysis (STA), timing closure, clock‑domain crossing (CDC) correctness, and constraint quality
• - Debug designs through simulation, Signal Tap / on‑chip debug, and lab bring‑up as required
• - Contribute to design examples, simulation models, and technical documentation for internal and customer use

• - Work effectively within engineering infrastructure including Perforce, Git Hub, Jenkins, and Team City
• - Support continuous integration, regression flows, and release quality for IP and reference designs
• - Collaborate with software, systems, and applications engineers on HW/SW co‑design and platform integration, including robotics software stacks where applicable (e.g. ROS2)
• - Support platform bring‑up, validation, and resolution of customer or internal technical issues

• - Min 10 + Years experience with BSc / MSc (or equivalent) in Electrical/Electronic Engineering (EEE), Computer Engineering, Computer Science, or a related discipline
• - Strong production experience in RTL design (Verilog and/or System Verilog) targeting FPGAs
• - Hands‑on experience with RTL verification and simulation (e.g. Model Sim/Questa, VCS, or equivalent)
• - Proven ability to close timing and optimize resource utilization on real FPGA designs
• - Working knowledge of Quartus Prime and Platform Designer (or equivalent FPGA toolchain and system integration flows)
• - Experience debugging FPGA designs using on‑chip instrumentation (e.g. Signal Tap Logic Analyzer) and hands‑on bring‑up and debug on development kits and physical boards
• - Familiarity with modern engineering infrastructure such as Perforce and/or Git…