ASIC Design Verification Engineer II; Co-Op

Meet the Team

Acacia, now part of Cisco, provides innovative silicon‑based high speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs and coherent modules empower cloud and service providers to meet the fast‑growing demand for data. We have assembled a team of cross‑functional experts capable of solving the challenges of next generation optical interconnects, resulting in industry‑leading, award‑winning products.

Come join us at Cisco, named the #1 world’s best workplace, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

The ASIC Design Verification Co‑Op Engineer will be a member of a team working on next generation 100G‑1T coherent optical communications products. This role is focused on verifying highly‑complex ASICs that are used in these next‑generation telecom systems. The engineer in this role uses sophisticated verification techniques to complete advanced individual contributions to the projects. There are opportunities to develop process improvements for the team and to coordinate with other engineers within the engineering community to add value to the ASIC projects.

This engineer must be a fast‑learning, self‑motivated effective person who is able to operate in a fast‑paced, dynamic and highly technical environment. A successful candidate will be energetic, collaborative and passionate about learning how to deliver the most advanced high speed optical products in the world. Knowledge of object‑oriented verification methodologies is required.

• Develop detailed and comprehensive test plans
• Develop verification test benches
• Timely execution of test plans
• Assist with chip level design tradeoffs by working with design engineers
• Participate in review of design verification coding and coverage metrics
• Participate and assist in FPGA emulation efforts
• Work collaboratively with team to develop & incorporate latest technologies & processes

• Currently enrolled in a full‑time graduate program
• Knowledge of the latest ASIC verification methodologies, tools and scripting/programming languages
• Knowledge of System Verilog/UVM, SystemC
• Knowledge of C and/or C++

• Knowledge of DSP algorithms and modulation techniques such as QAM
• Lab silicon validation experience
• Knowledge of Formal Verification methodologies and tools such as Jasper
• Ability to work collaboratively across business groups
• Excellent communication skills (verbal and written)

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