Hardware FPGA Design Engineer - Acacia; Hybrid

The application window is expected to close on: 1/31/25

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

This is a hybrid role with three days per week at Cisco's Maynard, MA office.

Acacia, now part of Cisco, designs intelligent optical transceivers using sophisticated signal processing and photonic integration for >1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. The team is a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Software, Optics, and manufacturing teams.

• Design/Verify FGPAs For Acacia's Product and Evaluation platform
• Write Python routines for Test Development and Automation
• Contribute to FPGA Emulation of ASIC Blocks
• Contribute to our custom ASIC RTL code

• Bachelors +8 years of experience, or Masters +6 years of experience, or PhD +3 years of experience of related experience or higher with minimum
• 5+ years of FPGA design and verification experience
• Experience in Verilog RTL coding and synthesis for FPGAs
• Experience with Python and Linux
• Experience designing interfaces with Processors, SPI & I2C devices, MDIO, high speed SERDES, etc.
• Experience in Xilinx® design tool chain for design, place, and route (ISE®, Vivado® suite)

• C/C++ and experience coding with embedded MCUs
• Experience in designs and timing closure with multiple clock domains
• Experience work in labs and experience with test equipment to help with board level and FPGA bring up
• Experience with analog components (OpAmps, DACs/ADCs, etc.)
• Experience implementing digital control loops and DSP functions
• Experience with Xilinx FPGA families such as Ultrascale+
• Experience with Synopsys VCS simulation and Synplify® synthesis tools for FPGAs
• Expertise in creating FPGA implementation s from ASIC RTL code
• Expertise in digital design of standard cell ASICs
• Experience presenting technical information to technical and non-technical audiences.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following…