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Signal Integrity Engineer, Infrastructure Hardware

Job in Menlo Park, San Mateo County, California, 94029, USA
Listing for: Meta
Full Time position
Listed on 2026-10-18
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Electronics Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 180000 - 240000 USD Yearly USD 180000.00 240000.00 YEAR
Job Description & How to Apply Below
# Signal Integrity Engineer, Infrastructure Hardware Menlo Park, CA Engineering+ 2 more Apply nowMeta's infrastructure hardware team is seeking a Staff Signal Integrity Engineer to drive the design and validation of high-speed interconnects across Meta's data center platforms. In this role, you will own the signal integrity methodology, design, analysis, and validation for next-generation AI, networking, compute, and storage platforms, ensuring reliable high-speed data transmission across Ethernet, PCIe, DDR, and optical interconnect interfaces.

You will define SI/PI standards, guide platform architecture decisions, and collaborate closely with industry partners, hardware design, and silicon teams to deliver infrastructure at the scale Meta's global data centers demand.

---## Signal Integrity Engineer, Infrastructure Hardware Responsibilities
* Develop next-generation SI/PI solutions across a broad range of Meta platforms, including AI, network, compute, and storage systems
* Perform signal integrity simulations, implementation, validation, and test methodologies at the platform, board, and system levels using industry-standard tools such as HSpice, ADS, or Sigrity to validate channel performance and margins
* Develop and maintain channel models, IBIS-AMI models, and S-parameter extraction workflows for board-level and system-level SI analysis including end-to-end electrical-optical-electrical channels
* Define the next generation of open on- and off-chip interconnect technologies and integrate these into highly scalable, deployable, and maintainable systems
* Collaborate with design and manufacturing teams to define stackup requirements, routing constraints, via structures, and impedance targets for multi-layer high-speed designs
* Drive lab correlation and validation activities, including TDR, VNA, and oscilloscope-based measurements, to verify simulation accuracy and characterize channel performance
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