Senior -Speed PCB Designer PCIe Gen 6 & DDRHDI
Listed on 2026-10-18
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Engineering
Electronics Engineer, Hardware Engineer
CBL Solutions in Menlo Park, CA, seeks an experienced PCB Layout Engineer to own end-to-end layout for high-density server-board designs and high-speed interfaces, using Cadence Allegro. You will drive impedance control, length matching, and crosstalk mitigation on memory and PCIe interfaces (Gen5/6).
The role collaborates with EEs and ME engineers to meet manufacturability and reliability standards. Ideal candidates bring 5+ years of CAD experience, HDI microvia know-how, and a track record in
Are you ready to take on the Senior High-Speed PCB Designer for PCIe Gen 6 & DDR5 HDI role at CBL Solutions?
Join us at CBL Solutions as our next Senior High-Speed PCB Designer for PCIe Gen 6 & DDR5 HDI in Menlo Park, CA, United States.
We are currently recruiting a Senior High-Speed PCB Designer for PCIe Gen 6 & DDR5 HDI for our team in Menlo Park, CA, United States.
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