Senior Physical Design Engineer

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers.

With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at  and on Linked In and X.Senior Physical Design Engineer Locations:
Limerick, Ireland;
Edinburgh, Scotland About Analog Devices (ADI)
Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure, and connect.

Analog Devices is seeking a senior physical design engineer for its Data Center & Energy (DCE) group. Within DCE, we deliver high‑reliability power, connectivity, and analytics solutions for modern data centers and energy infrastructure.

The successful candidate will own and execute the physical implementation of complex mixed-signal SoCs, from floor planning through signoff. The role spans multiple process nodes—from mature analog processes through advanced deep-submicron FinFET technologies—and involves close collaboration with RTL designers, analog layout teams, and verification engineers to deliver silicon that meets aggressive performance, power, and area targets.

This is a demanding multi-disciplinary position with unique growth potential. The group culture aims to foster a challenging, exciting, and supportive environment. The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment. Analog Devices rewards performance, innovation, and collaboration.

Responsibilities include, but are not limited to:

Drive physical implementation from RTL handoff through GDSII signoff, including floor planning, power planning, placement, clock tree synthesis, routing, and timing closure

Perform and close static timing analysis across PVT corners; resolve timing violations with design and layout teams

Develop and maintain robust power delivery networks; perform IR-drop and electromigration analysis and drive fixes to closure

Execute physical verification (DRC, LVS, antenna, ERC) and resolve issues to achieve clean signoff

Collaborate with analog layout engineers on mixed-signal integration, including floorplan co-optimization and constraint development for sensitive analog/digital boundaries

Support design-for-test (DFT) insertion, scan chain stitching, and ATPG pattern generation

Contribute to flow development, methodology improvements, and automation of physical design tasks

Support silicon bring-up and debug; correlate physical design decisions with lab measurements

Minimum Qualifications:

BS in Electrical or Computer Engineering (or equivalent)4+ years of experience in ASIC/SoC physical design and implementation

Strong proficiency with Cadence digital implementation tools (Genus, Innovus, Tempus, Conformal, Voltus, Pegasus)
Solid understanding of static timing analysis, clock domain crossing, and multi-corner multi-mode signoff

Experience with mature analog process nodes (e.g., 180nm BCD) in addition to advanced digital nodes

Experience with power analysis (IR-drop, EM) and power intent specification (UPF/CPF)
Working knowledge of DFT methodologies (scan insertion, compression, ATPG, JTAG/boundary scan)
Proficiency in scripting for automation and flow development (Tcl, Python, shell)
Strong problem-solving skills and ability to work independently with minimal supervision

Good organization; written and verbal communication skills

Preferred Qualifications:

MS in Electrical or Computer Engineering (or equivalent)

Experience with mixed-signal SoC physical design, including analog/digital co-integration and constraint management

Experience with advanced process node physical design (deep submicron FinFET technologies)

Experience…