Process Engineer

San Francisco Bay Area, California, United States Hardware

Join Apple's ATG Sensing Group as a Senior Electronic Packaging Engineer to drive the development of innovative module packaging solutions for new consumer products. In this role, you will own the process development of New Product Introduction, architecting new concepts and defining process flows to ensuring successful high-volume manufacturing with external OSAT partners. You will work at the intersection of design, materials science, and manufacturing, collaborating with internal cross-functional teams and external suppliers to solve complex integration challenges and successfully bring next-generation sensing technologies to market.

This position requires a candidate with a proven track record of shipping products, deep technical expertise in assembly processes, and strong leadership skills.

Apple’s ATG Sensing Group is looking for a senior level electronic packaging engineer to work on developing exciting new products. This role will be responsible for providing module packaging solutions to be integrated in systems for consumer markets. This role will be working with internal device design, product design, operation, as well as external suppliers to develop and deploy new packaging technologies.

We are looking for individuals who are innovative as well as experienced in a high volume manufacturing environment. A successful candidate should have a proven track record of successfully shipped products with 3rd party manufacturing partners. Candidate must demonstrate the ability to lead cross functional teams to success. Candidate should be experienced with operating independently as well as collaboratively in a complex multi-disciplinary development program.

• Ownership of process equipment definition, process material selection, and process flow design for module packaging.
• Own existing projects packaging process and materials. Evaluate process and materials impact of module packaging with system integration.
• Develop new package process concepts to realize new module designs base on unique system requirements. Develop new package processes from Proof-of-Concept demonstrations to full production implementation.
• Collaborate with reliability team and product design team to identify design and process issues with the use of FMEA.
• Deep integration of simulations to validate design impact of process ahead of initiating process development.
• Establish communication channels with module integrators and any key technical suppliers to accomplish project success.
• Consolidate Major Issues List for each project to communicate with both internal and external parties.
• Collaborate with program management teams to accomplish timely delivery of project.
• Hand-off projects from engineering phase to operations team with clearly defined goals and deliverables.
• Present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.
• Have passion in semiconductor packaging technology, self motivated, can go deep, and be able to deliver under minimal supervision.
• Leveraging AI to improve overall project efficiency.

• BS and 10 +years of relevant industry experience.

• Understand and keep up-to-date with industry landscape on relevant technologies.
• Strong interpersonal and team-building skills.
• Proven track record of work with OSAT to bring up a product from conceptual to MP stage.
• Strong materials science and failure analysis (FA) knowledge related to assembly chip-packaging interactions and reliability failures.
• Proficient in applying DOE vs. Hypothesis tool for root cause analysis.
• Excellent written and verbal communication skills.
• In-depth knowledge in the area of semiconductor sensor packaging technologies.
• Expert-level knowledge in assembly steps: wafer thinning, wafer dicing, die attach (including flip chip and multi-die stacking), wirebond, encapsulation and underfill, SMT, transfer/compression molding, singulation, and wafer level packaging processes.
• Working level knowledge in wafer bumping, RDL, and TSV.
• Experience in using simulation to guide process setup.
• E…