Senior ASIC Verification Engineer

Senior ASIC Verification Engineer – NVIDIA Clocks Team

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The team is committed to delivering high‑quality clocking and reset logic to various units in SOC and GPU ASIC. The complexity of the clocks and resets design has increased many folds, requiring sophisticated verification to deliver a bug‑free clocks design across Data Centers, Consumer graphics, Self‑driving cars, and the growing field of artificial intelligence.

Modern clocking verification solutions must be innovative, ensure quality in covering the complex design specifications, and balance constraints on infrastructure, re‑usability, testing speed and multi‑platform support.

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop a scalable solution that works across platform.
• Hands‑on industry‑standard tools and state‑of‑the‑art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
• Partner closely with our clocks architecture and design team to validate our clocks design.
• Coordinate with internal and external teams across time zones.

• BS or MS in EE/ECE or equivalent experience.
• 5+ years of relevant industry work experience.
• Good understanding of Logic Design and Architecture.
• Expertise in industry‑standard verification flows like SV constraint‑random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Exposure on block level and system‑level verification.
• Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
• Ability to collaborate and work with multiple groups.
• Prior experience in implementing Test plans for pre‑silicon platforms.
• Understanding of DFT/IST is optional.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000–$212,750 for Level 3, and $168,000–$264,500 for Level 4. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until December 12, 2025.

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.